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IDT72V36100 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72V36100 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 48 page  6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 PIN DESCRIPTION (TQFP AND PBGA PACKAGES) Symbol Name I/O Description BM(1) Bus-Matching I BMworkswithIWandOWtoselectthebussizesforbothwriteandreadports. SeeTable1forbussizeconfiguration. BE(1) Big-Endian/ I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will Little-Endian selectLittle-Endianformat. D0–D35 DataInputs I Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state. EF/OR EmptyFlag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. OutputReady InFWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs. FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the Input Ready FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FSEL0(1) FlagSelectBit0 I DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheprogrammable flags PAE and PAF. There are up to eight possible settings available. FSEL1(1) FlagSelectBit1 I DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheprogrammable flags PAE and PAF. There are up to eight possible settings available. FWFT/SI FirstWordFall I DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispin functions Through/Serial In asaserialinputforloadingoffsetregisters. HF Half-FullFlag O HF indicates whether the FIFO memory is more or less than half-full. IP(1) InterspersedParity I DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.A HIGHwillselectInterspersedParity mode.InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnot effect the data written to and read from the FIFO. IW(1) InputWidth I This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration. LD Load I Thisisadualpurposepin.DuringMasterReset,thestateoftheLD inputalongwithFSEL0andFSEL1,determines oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe offsetregisters. OE OutputEnable I OE controls the output impedance of Qn. OW(1) OutputWidth I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration. MRS MasterReset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes. PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset Almost-EmptyFlag register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n. PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the Almost-FullFlag Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. PFM(1) Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM Flag Mode willselectSynchronousProgrammableflagtimingmode. PRS PartialReset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. Q0–Q35 DataOutputs O Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care state.Outputsarenot5VtolerantregardlessofthestateofOE. RCLK/ Read Clock/ I If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK RD Read Strobe reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW. Asynchronous operation of the RCLK/RD input is only available in the PBGA package. REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers. RM(1) RetransmitTiming I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select Mode normallatencymode. RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable flagsettings.RT isusefultorereaddatafromthefirstphysicallocationoftheFIFO. NOTE: 1. Inputs should not change state after Master Reset. |
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