8

COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641

3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36

is complete, the X and Y register values are loaded bitwise through the FS0/

SDinputoneachLOW-to-HIGHtransitionofCLKAthattheFS1/SENinputis

LOW. Thereare18-or20-bitwritesneededtocompletetheprogrammingfor

theIDT72V3631orIDT72V3641respectively. Thefirst-bitwritestoresthemost

significantbitoftheYregister,andthelast-bitwritestorestheleastsignificantbit

of the X register. Each register value can be programmed from 1 to 508

(IDT72V3631) or 1 to 1,020 (IDT72V3641).

WhentheoptiontoprogramtheOffsetregistersseriallyischosen,theInput

Ready(IR)flagremainsLOWuntilallregisterbitsarewritten. TheIRflagisset

HIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloadedtoallow

normal FIFO operation. The timing diagram for serial load of offset registers

can be found in Figure 4.

FIFO WRITE/READ OPERATION

Thestateoftheport-Adata(A0-A35)outputsiscontrolledbytheport-AChip

Select(CSA)andtheport-AWrite/Readselect(W/RA). TheA0-A35outputs

are in the high-impedance state when either CSA or W/RA is HIGH. The A0-

A35 outputs are active when both CSA and W/RA are LOW.

Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH

transitionofCLKAwhenCSA andtheport-AMailboxselect(MBA)areLOW,

W/RA,theport-AEnable(ENA),andtheInputReady(IR)flagareHIGH(see

Table 2). Writes to the FIFO are independent of any concurrent FIFO read.

For the Write Cycle Timing diagram, see Figure 5.

Theport-Bcontrolsignalsareidenticaltothoseofport-Awiththeexception

thattheport-BWrite/Readselect(W/RB)istheinverseoftheport-AWrite/Read

select (W/RA). The state of the port-B data (B0-B35) outputs is controlled by

the port-B Chip Select (CSB) and the port-B Write/Read select (W/RB). The

B0-B35outputsareinthehigh-impedancestatewheneitherCSBisHIGHor

W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB

is HIGH.

DataisreadfromtheFIFOtoitsoutputregisteronaLOW-to-HIGHtransition

ofCLKBwhenCSBandtheport-BMailboxselect(MBB)areLOW,W/RB,the

port-B Enable (ENB), and the Output Ready (OR) flag are HIGH (see Table

3). ReadsfromtheFIFOareindependentofanyconcurrentFIFOwrites. For

the Read Cycle Timing diagram, see Figure 6.

Thesetup-andhold-timeconstraintstotheportclocksfortheportChipSelects

andWrite/Readselectsareonlyforenablingwriteandreadoperationsandare

notrelatedtohigh-impedancecontrolofthedataoutputs. IfaportEnableisLOW

duringaclockcycle,theportChipSelectandWrite/Readselectmaychange

states during the setup- and hold time window of the cycle.

WhentheORflagisLOW,thenextdatawordissenttotheFIFOoutputregister

automaticallybytheCLKBLOW-to-HIGHtransitionthatsetstheORflagHIGH.

WhenORisHIGH,anavailabledatawordisclockedtotheFIFOoutputregister

onlywhenaFIFOreadisselectedbytheport-BChipSelect(CSB),Write/Read

select (W/RB), Enable (ENB), and Mailbox select (MBB).

SIGNAL DESCRIPTION

RESET

The IDT72V3631/72V3641 is reset by taking the Reset (RST) input LOW

for at least four port-A Clock (CLKA) and four port-B (CLKB) LOW-to-HIGH

transitions. TheResetinputmayswitchasynchronouslytotheclocks. Areset

initializesthememoryreadandwritepointersandforcestheInputReady(IR)

flagLOW,theOutputReady(OR)flagLOW,theAlmost-Empty(AE)flagLOW,

andtheAlmost-Full(AF)flagHIGH. ResettingthedevicealsoforcestheMailbox

Flags (MBF1, MBF2) HIGH. After a FIFO is reset, its Input Ready flag is set

HIGHafteratleasttwoclockcyclestobeginnormaloperation. AFIFOmustbe

reset after power up before data is written to its memory. The relevant FIFO

Reset timing diagram can be found in Figure 2.

FIRST WORD FALL THROUGH MODE (FWFT)

These devices operate in the First Word Fall Through mode (FWFT). This

modeusestheOutputReadyfunction(OR)toindicatewhetherornotthereis

validdataatthedataoutputs(B0-B35).ItalsousestheInputReady(IR)function

toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting. In

the FWFT mode, the first word written to an empty FIFO goes directly to data

outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby

performingaformalreadoperation.

ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-

MING

TworegistersinthesedevicesareusedtoholdtheoffsetvaluesfortheAlmost-

Empty and Almost-Full flags. The Almost-Empty (AE) flag Offset register is

labeledX,andtheAlmost-Full(AF)flagOffsetregisterislabeledY. TheOffset

registercanbeloadedwithavalueinthreeways:oneoftwopresetvaluesare

loadedintotheOffsetregisters,parallelloadfromportA,orserialload. TheOffset

registerprogrammingmodeischosenbytheflagselect(FS1,FS0)inputsduring

a LOW-to-HIGH transition on the RST input (See Table 1).

— PRESET VALUES

Ifthepresetvalueof8or64ischosenbytheFS1andFS0inputsatthetime

of a RST LOW-to-HIGH transition according to Table 1, the preset value is

automaticallyloadedintotheXandYregisters. Nootherdeviceinitializationis

necessarytobeginnormaloperation,andtheIRflagissetHIGHaftertwoLOW-

to-HIGHtransitionsonCLKA.ForthePresetvalueloadingtimingdiagram,see

Figure 2.

— PARALLEL LOAD FROM PORT A

To program the X and Y registers from port A, the device is reset with FS0

and FS1 LOW during the LOW-to-HIGH transition of RST. After this reset is

complete,theIRflagissetHIGHaftertwoLOW-to-HIGHtransitionsonCLKA.

ThefirsttwowritestotheFIFOdonotstoredatainitsmemorybutloadtheOffset

registers in the order Y, X. Each Offset register of the IDT72V3631 and

IDT72V3641 uses port-A inputs (A8-A0), (A9-A0), and (A10-A0), respec-

tively. Thehighestnumberinputisusedasthemostsignificantbitofthebinary

number in each case. Each register value can be programmed from 1 to 508

(IDT72V3631) and 1 to 1,020 (IDT72V3641). After both Offset registers are

programmedfromportA,subsequentFIFOwritesstoredataintheRAM. The

timing diagram for parallel load of offset registers can be found in Figure 3.

— SERIAL LOAD

To program the X and Y registers serially, the device is reset with FS0/SD

andFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRST. Afterthisreset

NOTE:

1. X register holds the offset for AE; Y register holds the offset for AF.

FS1

FS0

RST

HH

↑

Serial Load

HL

↑

64

LH

↑

8

LL

↑

Parallel Load From Port A

TABLE 1 —

—

—

—

— FLAG PROGRAMMING