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72V3631L15PFG Datasheet(PDF) 5 Page - Integrated Device Technology |
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72V3631L15PFG Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 20 page 5 COMMERCIALTEMPERATURERANGE IDT72V3631/72V3641 3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36 Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3641 with CLKA and CLKB set tofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnectedtonormalize thegraphtoazero-capacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3631/72V3641inputsdrivenbyTTLHIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x ICC(f) + Σ(CL x VCC2 x fO) N where: N = number of outputs = 36 CL = outputcapacitanceload fO = switchingfrequencyofanoutput When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT = VCC x fS x 0.025 mA/MHz 0 10 20 3040 5060 70 0 25 50 75 100 125 150 VCC = 3.3V fS Clock Frequency MHz fdata = 1/2 fS TA = 25 °C CL = 0 pF VCC = 3.0V VCC = 3.6V 4658 drw 04 175 |
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