4

General Specifications

Feature

Value

Interface

IC 100kHz

Input color format

CIE XYZ, Yxy, Yu’v’ and RGB (illuminant E)

Input sensor signal

0 to .5V (typical configuration)

Minimum dynamic range

Sensor output > 500 (ADC output code, each channel) during calibration

Output PWM frequency

610Hz nominal (typical configuration)

Output PWM resolution

1 bits

Error flag

Assertion on ERR_FLAG pin indicates an error condition

Device address control

Upper 5 bits 10101 binary, lower  bits defined by A1:A0 pins in that order

Supply

5V digital, 5V analog (nominal)

I/O

Schmitt-CMOS input and CMOS/TTL compatible output

PWM_R, PWM_G, PWM_B (Pin 16, Pin 15, Pin 14)

The PWM_R, PWM_G, and PWM_B output pins drive the

external LED drivers that drive the LED arrays. Typically

PWM_R drives only the red LEDs, PWM_G drives only the

green LEDs and PWM_B drives only the blue LEDs. They

are the output enable signals of the red, green and blue

LED drivers. So, they control the on-time duration of the

LEDs.

The assertion level of the PWM* signals can be toggled

by the user to support both active-low and active-high

enable inputs pins at the LED driver side. This is done by

configuring the PWML bit of register CONFIG1.

ERR_FLAG (Pin 17)

The ERR_FLAG pin is asserted high when an error condi-

tion is detected. The user can determine the type of error

by reading the ERROR register. The error conditions are

described in the ‘High Level Description’ section.

SENSE_X, SENSE_Y, SENSE_Z (Pin 23, Pin 22, Pin

21)

The SENSE_X, SENSE_Y and SENSE_Z pins are analog in-

put pins which are tied to the X-channel, Y-channel and

Z-channel of the photosensor output respectively. An

averaging filter is placed in between the sensor output

and the SENSE_X, SENSE_Y and SENSE_Z pins. The filter is

typically a 68kohm-1uF single-pole low-pass filter.

VREF_EXT (Pin 20)

The VREF_EXT pin is an analog input pin, which provides

an external reference voltage for the ADC. Typically, users

will use the internal reference generator to operate the

ADC. However, in specific application conditions, an ex-

ternal reference may be required. The external reference

is enabled by setting the VREFS bit of register CONFIG1

high.

ROSC (Pin 19)

A 68kohm precision 1% resistor is connected from the

ROSC to AVSS pin for use by the internal oscillator. In

external clock mode, ROSC can be left floating.

(Refer to the Application Note 5070 for resistor selection).

DVDD, DVSS, AVDD, AVSS (Pin 12, Pin 13, Pin 24,

Pin 18)

QDJD-J821 has separate power ground nets for the ana-

log and digital section. A star connection from a central

power source is recommended when designing the wir-

ing to these supply pins.

DVDD = Digital positive supply

DVSS = Digital ground

AVDD = Analog positive supply

AVSS = Analog ground