QDJD-J821-SCR00 datasheet(11/15 Pages) AVAGO

Part #	QDJD-J821-SCR00

Description	Robust CMOS-Schmitt input

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Manufacturer	AVAGO [AVAGO TECHNOLOGIES LIMITED]

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11

Figure 6. Master-Receiver Acknowledge

SCL

(MASTER)

8

9

SDA

(SLAVE-TRANSMITTER)

SDA

(MASTER-RECEIVER)

Acknowledge

clock pulse

LSB

SDA left HIGH

by transmitter

Not

acknowledge

SDA left HIGH

by receiver

P

Sr

STOP or repeated

START condition

Figure 7. Slave Addressing

MSB

LSB

R/W

A1

A6

A5

A4

A3

A2

A0

Slave address

1

0

1

In the case of the master-receiver and slave-transmitter,

the master generates a not acknowledge to signal the

end of the data transfer to the slave-transmitter. The mas-

ter can then send a STOP or repeated START condition to

begin a new data transfer.

In all cases, the master generates the acknowledge or not

acknowledge SCL clock pulse.

See Figure 6.

Addressing

Each device on the I2C bus needs to have a unique ad-

dress. This is the first byte that is sent by the master-trans-

mitter after the START condition. The protocol defines the

address as the first seven bits of the first byte.

The eighth bit or least significant bit (LSB) determines

the direction of data transfer. A ‘one’ in the LSB of the

first byte indicates that the master will read data from

the addressed slave (master-receiver and slave-transmit-

ter). A ‘zero’ in this position indicates that the master will

write data to the addressed slave (master-transmitter and

slave-receiver).

A device whose address matches the address sent by the

master will respond with an acknowledge for the first

byte and set itself up as a slave-transmitter or slave-re-

ceiver depending on the LSB of the first byte.

The slave address in QDJD-J821 is made up of a fixed

part and a programmable part. The fixed part is A6 to A2

and is set as shown in Figure 7. The programmable part

is A1 and A0, which is set by external package pins. The

programmable address pins allows a maximum of four

QDJD-J821 chips on the same I2C bus to be addressed

(address range from 54h to 57h).

See Figure 7.

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QDJD-J821-SCR00 Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED

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