CY7C408A-409A datasheet(10/16 Pages) CYPRESS

Part #	CY7C408A-409A

Description	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C408A

CY7C409A

10

Figure 5. Depth and Width Expansion[23,24,25,26,27].

Notes:

22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the

devices.

23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output.

24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until

the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for

one internal cycle (at least tPOR) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will

line up behind the first word and will not appear on the outputs until SO has been brought LOW.

26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW.

27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output

ready flags. This need is due to the variation of delays of the FIFOs

28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used.

29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring.

The complement of this holds when data is shifted out as a packet.

192 x 27 Configuration

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

COMPOSITE

OUTPUT READY

SHIFT OUT

MR

COMPOSITE

INPUT READY

SHIFT IN

C408A–21

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

HF/AFE

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

DO4

DI4

DI5

DI6

DI7

DI8

DO5

DO6

DO7

DO8

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