MCP37220-200 datasheet(8/116 Pages) MICROCHIP

Part #	MCP37220-200

Description	Output Data Format

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Manufacturer	MICROCHIP [Microchip Technology]

Direct Link	http://www.microchip.com

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8 / 116 page

MCP37210-200 AND MCP37D10-200

DS20005395B-page 8

 2015-2016 Microchip Technology Inc.

Notes:

1.

These pins are for the internal reference voltage output. They should not be driven. External decoupling circuit

is required. See Section 4.3.3 “Decoupling Circuits for Internal Voltage Reference and Bandgap Output”

for details.

2.

When VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-tap of

a balun), VCM pin should be decoupled with a 0.1 µF capacitor.

3.

ADR1 (for A1 bit) is internally bonded to GND (‘0’). If ADR0 is dynamically controlled, ADR0 must be held

constant while CS is “Low”.

4.

The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits the Reset

mode, initializes all internal user registers to default values and begins power-up calibration.

5.

CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has

completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a

Soft Reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain

the prior condition.

6.

The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is

controlled differently depending on the configuration of the digital signal post-processing (DSPP) and PLL (or

DLL). See also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.

7.

DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for

“Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The even

data bits (Q0, Q2, Q4, Q6, Q8, Q10) appear when DCLK+ is “High”. The odd data bits (Q1, Q3, Q5, Q7, Q9, Q11)

appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68 (Register 5-26) for output polarity

control. See Figure 2-2 for LVDS output timing diagrams.

8.

OVR: OVR will be held “High”’ when analog input overrange is detected. Digital signal post-processing (DSPP)

will cause OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.

WCK: Available for the I/Q output mode only in the MCP37D10. WCK is normally “Low” in I/Q output mode, and

“High” when it outputs in-phase (I) data.

(a) MCP37210 and MCP37D10 operating outside I/Q output mode: WCK/OVR+ is OVR, and WCK/OVR- is

logic ‘0’ (not used). In DDR LVDS output mode, the rising edge of DCLK+ is OVR.

(b) I/Q output mode in MCP37D10: In CMOS output mode, WCK/OVR+ is OVR and WCK/OVR- is WCK. WCK

is synchronized to in-phase (I) data. In DDR LVDS output mode, WCK/OVR+ and WCK/OVR- are multiplexed.

The rising edge of DCLK+ is OVR and the falling edge is WCK.

9.

This pin function is not released yet.

Pins that need to be grounded

A24, A64,

B20, B54

GND

These pins are not supply pins, but need to be tied to ground.

Output Test Pins

A28 - A29, A31,

B23, B25, B26

TP

Digital

Output

Output test pins. Do not use. Always leave these pins floating. Do not

tie to ground or supply.

TABLE 1-1:

PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)

Pin No.

Name

I/O Type

Description

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