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DSP96002FE60 Datasheet(PDF) 4 Page - Motorola, Inc |
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DSP96002FE60 Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 111 page DSP96002 Product Documentation iv DSP96002/DRev. 2 MOTOROLA – Off-chip expansion to 2 × 232 32-bit words of data memory – Off-chip expansion to 232 32-bit words of program memory • Miscellaneous features – Two expansion ports assignable to X data, Y data, or program memory spaces or a combination thereof, effectively doubling off-chip bus bandwidth. – Host interface circuitry on each port provides a flexible slave interface to Direct Memory Access (DMA) controllers and external processors for easy design of multimaster systems – Write strobe pins support interface to external SRAMs without additional logic – Two programmable timers/counters – Three external interrupt/mode control lines – One external reset line for hardware reset – 4-pin OnCE port for unobtrusive, processor speed-independent debugging – HCMOS design for operating frequencies from 60 MHz down to DC – 223-pin plastic Pin Grid Array (PGA) package or 240-pin Ceramic Quad Flat Pack (CQFP) package – 5.0 V power supply PRODUCT DOCUMENTATION The two manuals listed in Table 1 are required for a complete description of the DSP96002 and are necessary to design properly with the device. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 1 Additional Documentation Document Name Description Order Number DSP96002 User’s Manual Detailed description of the DSP96002 core processor and peripherals DSP96002UM/AD DSP96002 Data Sheet Electrical and timing specifications, and pin and package descriptions DSP96002/D Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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