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SEC1210-A5-02NC Datasheet(PDF) 6 Page - Microchip Technology |
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SEC1210-A5-02NC Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 218 page  SEC1110/SEC1210 DS00001561C-page 6 2013 - 2016 Microchip Technology Inc. 1.3 USB Subsystem The USB Subsystem is made up of the following 3 functional blocks • FS USB PHY • USB Device Controller (UDC) • Interface Bridge with USB endpoint buffers 1.3.1 FS USB PHY AND DEVICE CONTROLLER The FS USB PHY contains the D+ pull-up resistor and handles the reception of USB data. The D+ and D- signals are passed through the differential receiver (which is external to the device controller core) to get a single-ended bit stream. The device controller has a digital phase-locked loop (DPLL) to extract the clock and data information. The clock and data are passed to the SIE (serial interface engine) block to identify the sync pattern and for NRZI-NRZ conversion. This NRZ data is then passed through a bit-stripper which strips off excessive inserted zeros. The data stream is passed through a PID decoder and checker to identify different PID’s. The SIE block handles the protocol according to the type of PID and the endpoint to which the current transaction is addressed. If it is a data PID, the serial data is assembled into byte format and the received data is CRC is checked, then put into a one-byte buffer. The protocol layer takes the data from the buffer and forwards it to the Interface Bridge. On control transfers to endpoint 0, the protocol layer forwards the transfers to the endpoint block. If the application violates the data transfer protocol during the transfer of data from the buffer to the application bus, the protocol layer controls the SIE to recover from this error. 1.3.2 INTERFACE BRIDGE AND ENDPOINT BUFFERS These act as the interface between the 8051 micro controller and the USB device controller. The USB endpoint buffers are memory mapped on the 8051 XDATA bus. A simple buffer scheme is employed, which assigns a single/ping-pong buffer to each USB endpoint for ease of software control. Each buffer must be cleared before the next data transfer can be started. When USB OUT data is received, it is placed into the appropriate OUT endpoint buffer and the 8051 is signaled with an interrupt (polling is also available) When an IN request is received, the 8051 is signaled with an interrupt and the 8051 will transfer data to the appropriate IN endpoint buffer and set a ready flag. The data will automatically be encoded for transfer over the USB bus. 1.4 Power Management Unit The programmable clock divider supports division of the 48 MHz main clock. Additionally it enables power down under program or hardware control. Exit from power down is accomplished through a single input pin. The power management methods employed will enable a USB Suspend current of 200 A typical (400 A typical including Rpu current). In STOP Mode, 1 A is the maximum current for a bare bones design. FIGURE 1-1: USB SUBSYSTEM BLOCK USB FS PHY USB 1.1 Device Controller Interface Bridge + Endpoint Buffers USB D+ USB D- XDATA Interrupt |
Similar Part No. - SEC1210-A5-02NC |
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