Documentation Errata

DSP56311 Device Errata for Mask 1K34A, Rev. 5

Freescale Semiconductor

11

ED34

Description (added 1/5/99; identified as a Documentation errata 2/1/99):

When stack extension is enabled, the read result from stack may be improper if two

previous executed instructions cause sequential read and write operations with SSH.

Two cases are possible:

Case 1:

For the first executed instruction: move from SSH or bit manipulation on SSH (i.e.

jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

For the second executed instruction: move to SSH or bit manipulation on SSH (i.e.

jsr, bsr, jscc, bscc).

For the third executed instruction: an SSL or SSH read from the stack result may be

improper - move from SSH or SSL or bit manipulation on SSH or SSL (i.e., bset,

bclr, bchg, jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

Workaround:

Add two NOP instructions before the third executed instruction.

Case 2:

For the first executed instruction: bit manipulation on SSH (i.e. bset, bclr, bchg).

For the second executed instruction: an SSL or SSH read from the stack result may

be improper - move from SSH or SSL or bit manipulation on SSH or SSL (i.e., bset,

bclr, bchg, jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

Workaround:

Add two NOP instructions before the second executed instruction.

Pertains to:

DSP56300 Family Manual, Appendix B, add a new section called

“Stack Extension Enable Restrictions.” Cover all cases. Also, in Section 6.3.11.15,

add a cross reference to this new section.

1K34A

ED38

Description (added 7/14/99):

If Port A is used for external accesses, the BAT bits in the AAR3-0 registers must be

initialized to the SRAM access type (i.e. BAT = 01) or to the DRAM access type

(i.e. BAT = 10). To ensure proper operation of Port A, this initialization must occur

even for an AAR register that is not used during any Port A access. Note that at

reset, the BAT bits are initialized to 00.

Pertains to:

DSP56300 Family Manual, Port A Chapter (Chapter 9 in Revision 2),

description of the BAT[1 –0] bits in the AAR3 - AAR0 registers. Also pertains to

the core chapter in device-specific user’s manuals that include a description of the

AAR3 - AAR0 registers with bit definitions (usually Chapter 4).

1K34A