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K7N323601M-QC20 Datasheet(PDF) 4 Page - Samsung semiconductor |
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K7N323601M-QC20 Datasheet(HTML) 4 Page - Samsung semiconductor |
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4 / 18 page  1Mx36 & 2Mx18 Flow-Through NtRAMTM - 4 - Rev 2.0 Nov. 2003 K7M321825M K7M323625M PIN CONFIGURATION(TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin TQFP (20mm x 14mm) DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 Vss VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa PIN NAME Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. A0 - A19 ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control 32,33,34,35,36,37,43 4445,46,47,48,49,50, 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Output Power Supply (2.5V or 3.3V) Output Ground 15,16,41,65,91 14,17,40,66,67,90 38,39,42 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 K7M323625M(1Mx36) VSS |
Similar Part No. - K7N323601M-QC20 |
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Similar Description - K7N323601M-QC20 |
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