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72V03L25JG8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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72V03L25JG8 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 12 page 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9 OPERATING MODES: Caremustbetakentoassurethattheappropriateflagismonitoredbyeach system (i.e. FFis monitored on the device where Wis used; EFis monitored onthedevicewhereRisused).Foradditionalinformation,refertoTechNote 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. SINGLE DEVICE MODE A single IDT72V01/72V02/72V03/72V04/72V05/72V06 may be used when the application requirements are for 512/1,024/2,048/4,096/8,192/ 16,384wordsorless.ThesedevicesareinaSingleDeviceConfigurationwhen the Expansion In ( XI) control input is grounded (see Figure 12). TheseFIFOscaneasilybeadaptedtoapplicationswhentherequirements are for greater than 512/1,024/2,048/4,096/8,192/16,384 words. Figure 14 demonstratesDepthExpansionusingthreeIDT72V01/72V02/72V03/72V04/ 72V05/72V06s. Any depth can be attained by adding additional IDT72V01/ 72V02/72V03/72V04/72V05/72V06s. These devices operate in the Depth Expansionmodewhenthefollowingconditionsaremet: 1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(FL)control input. 2. All other devices must have FLin the HIGH state. 3. TheExpansionOut(XO)pinofeachdevicemustbetiedtotheExpansion In ( XI ) pin of the next device. See Figure 14. 4. ExternallogicisneededtogenerateacompositeFullFlag(FF)andEmpty Flag ( EF). This requires the ORing of all EFs and ORing of all FFs (i.e. allmustbesettogeneratethecorrectcompositeFForEF). SeeFigure14. 5. The Retransmit ( RT) function and Half-Full Flag ( HF) are not available in the Depth Expansion Mode. Foradditionalinformation,refertoTechNote9: CascadingFIFOsorFIFO Modules. USAGE MODES: WIDTH EXPANSION Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput controlsignalsofmultipledevices. Statusflags(EF,FFandHF)canbedetected from any one device. Figure 13 demonstrates an 18-bit word width by using twoIDT72V01/72V02/72V03/72V04/72V05/72V06s. Anywordwidthcanbe attainedbyaddingadditionalIDT72V01/72V02/72V03/72V04/72V05/72V06s (Figure 13). BIDIRECTIONAL OPERATION Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72V01/72V02/72V03/72V04/72V05/72V06sasshowninFigure16.Both Depth Expansion and Width Expansion may be used in this mode. DATAFLOW-THROUGH Twotypesofflow-throughmodesarepermitted,areadflow-throughand writeflow-throughmode. Forthereadflow-throughmode(Figure17),theFIFO permitsareadingofasinglewordafterwritingonewordofdataintoanempty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W,calledthefirstwriteedge,anditremainsonthebusuntilthe Rlineisraised fromLOW-to-HIGH,afterwhichthebuswouldgointoathree-statemodeafter tRHZ ns. The EFline would have a pulse showing temporary deassertion and then would be asserted. Inthewriteflow-throughmode(Figure18),theFIFOpermitsthewritingof asinglewordofdataimmediatelyafterreadingonewordofdatafromafullFIFO. The Rline causes the FFto be deasserted but the Wline being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge ofW,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhenFF isnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer. |
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