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DSC-3966/5

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JUNE 2012

IDT72V81

IDT72V82

IDT72V83

IDT72V84

IDT72V85

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO

DUAL 512 x 9, DUAL 1,024 x 9

DUAL 2,048 x 9, DUAL 4,096 X 9

DUAL 8,192 X 9

2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The AsyncFIFO

™ isatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEATURES:

— Active: 330 mW (max.)

— Power-down: 18 mW (max.)

and functional flexibility

matching, and data sorting applications

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

TheIDT72V81/72V82/72V83/72V84/72V85aredual-FIFOmemoriesthat

loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctionaland

compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single

packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate

pins. The devices use Full and Empty flags to prevent data overflow and

underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth

word size and depth.

The reads and writes are internally sequential through the use of ring

pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data

istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead

(R) pins.

The devices utilize a 9-bit wide data array to allow for control and parity

bitsattheuser’soption.Thisfeatureis especiallyusefulindatacommunications

applicationswhereitisnecessarytouseaparitybitfortransmission/reception

errorchecking.ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset

of the read pointer to its initial position when RT is pulsed low to allow for

retransmission from the beginning of data. A Half-Full Flag is available in the

single device mode and width expansion modes.

TheseFIFOsarefabricatedusinghigh-speedCMOStechnology.Theyare

designed for those applications requiring asynchronous and simultaneous

read/writesinmultiprocessingandratebufferapplications.

FUNCTIONAL BLOCK DIAGRAM

WA

WRITE

CONTROL

READ

CONTROL

RA

FLAG

LOGIC

EXPANSION

LOGIC

XIA

WRITE

POINTER

RAM

ARRAY A

512 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA

OUTPUTS

RSA

FLA/RTA

XOA/HFA

FFA

EFA

WB

WRITE

CONTROL

READ

CONTROL

RB

FLAG

LOGIC

EXPANSION

LOGIC

XIB

WRITE

POINTER

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA

OUTPUTS

RSB

FLB/RTB

3966 drw 01

XOB/HFB

FFB

EFB

RAM

ARRAY A

512 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9