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72V01L25JG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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72V01L25JG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 12 page 1 JUNE 2012 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 IDT72V01, IDT72V02 IDT72V03, IDT72V04 IDT72V05, IDT72V06 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3033/7 FEATURES: ••••• 3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/ 7205/7206 family ••••• 512 x 9 organization (72V01) ••••• 1,024 x 9 organization (72V02) ••••• 2,048 x 9 organization (72V03) ••••• 4,096 X 9 organization (72V04) ••••• 8,192 x 9 organization (72V05) ••••• 16,384 X 9 organization (72V06) ••••• Functionally compatible with 720x family ••••• Low-power consumption — Active: 180 mW (max.) — Power-down: 18 mW (max.) ••••• 15 ns access time ••••• Asynchronous and simultaneous read and write ••••• Fully expandable by both word depth and/or bit width ••••• Status Flags: Empty, Half-Full, Full ••••• Auto-retransmit capability ••••• Available in 32-pin PLCC ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available ••••• Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM W WRITE CONTROL READ CONTROL R FLAG LOGIC EXPANSION LOGIC XI WRITE POINTER RAM ARRAY 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 16,384 x 9 READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS EF FF XO/HF RS FL/RT (D0-D8) 3033 drw 01 (Q0-Q8) DESCRIPTION: The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO memoriesthatoperateatapowersupplyvoltage(Vcc)between3.0Vand3.6V. Their architecture, functional operation and pin assignments are identical to those of the IDT7201/7202/7203/7204/7205/7206. These devices load and emptydataonafirst-in/first-outbasis.TheyuseFullandEmptyflagstoprevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead (R) pins. The devices have a maximum data access time as fast as 25 ns. Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits at the user’s option. This feature is especially useful in data communications applicationswhereitisnecessarytouseaparitybitfortransmission/reception errorchecking.TheyalsofeatureaRetransmit(RT)capabilitythatallowsfor resetofthereadpointertoitsinitialpositionwhenRTispulsedLOWtoallowfor retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. It has beendesignedforthoseapplicationsrequiringasynchronousandsimultane- ousread/writesinmultiprocessingandratebufferapplications. |
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