72V51233L5BBI datasheet(7/50 Pages) IDT

Part #	72V51233L5BBI

Description	3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION

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Manufacturer	IDT [Integrated Device Technology]

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES

(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FSYNC

PAFn Bus Sync

LVTTL

FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the

PAFn bus

(R3)

OUTPUT

during Polled operation of the

PAFn bus. During Polled operation each quadrant of queue status flags

is loaded on to the

PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads

device1 on to the

PAFnbusoutputs,thesecondWCLKrisingedgeloadsdevice2andsoon.Duringthe

WCLK cycle that a selected device is placed on to the

PAFn bus, the FSYNC output will be HIGH.

FXI

PAFn Bus

LVTTL

The FXI input is used when multi-queue devices are connected in expansion mode and Polled

PAFn

(T2)

Expansion In

INPUT

bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI

receives a token from the previous device in a chain. In single device mode the FXI input must be tied

LOW if the

PAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput

must be connected to the FXO output of the same device. In expansion mode the FXI of the first device

should be tied LOW, when direct mode is selected.

FXO

PAFn Bus

LVTTL

FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled

(T3)

Expansion Out

OUTPUT

PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This

pinpulsesHIGHwhendeviceNplacesits

PAFstatusontothePAFnbuswithrespecttoWCLK.Thispulse

(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first

quadrant of device N+1 will be loaded on to the

PAFn bus. This continues through the chain and FXO

of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the

chain provides synchronization to the user of this looping event.

ID[2:0](1)

Device ID Pins

LVTTL

For the 4Q multi-queue device the WRADD address bus is 5 bits and RDADD address bus is 6 bits wide.

(ID2-C9

INPUT

Whenaqueueselectiontakesplacethe3MSb’softhisaddressbusareusedtoaddressthespecificdevice

ID1-A10

(the LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s

ID0-B10)

of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected

in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which is

‘111’, however the ID does not have to match the device order. In single device mode these pins should

be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The

ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during

any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.

IW(1)

InputWidth

LVTTL

IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width

(L15)

INPUT

is x18, if HIGH then it is x9.

MAST(1)

Master Device

LVTTL

ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe

(K15)

INPUT

Master device or a Slave. If this pin is HIGH, the device is the master, if it is LOW then it is a Slave. The

master device is the first to take control of all outputs after a master reset, all slave devices go to

High-Impedance,preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,

this pin must be set HIGH.

MRS

Master Reset

LVTTL

Amasterresetisperformedbytaking

MRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired

(T9)

INPUT

aftermasterreset.

OE

OutputEnable

LVTTL

TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue

(M14)

INPUT

data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will

be in a Low Impedance condition if the

OE inputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe

in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be

inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpoint

OEprovidesthree-

state of that respective device.

OV

Output Valid Flag

LVTTL

Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice

(P9)

OUTPUT

data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That

is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the

OVflag

represents the data in that respective queue. When a selected queue on the read port is read to empty,

the

OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-

Impedance capability, required when multiple devices are used and the

OV flags are tied together.

OW(1)

OutputWidth

LVTTL

OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width

(L16)

INPUT

is x18, if HIGH then it is x9.

PIN DESCRIPTIONS (CONTINUED)

Symbol &

Name

I/O TYPE

Description

Pin No.

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72V51233L5BBI Datasheet(PDF) 7 Page - Integrated Device Technology

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