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AS29LV800T-120SI Datasheet(PDF) 1 Page - ANADIGICS, Inc |
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AS29LV800T-120SI Datasheet(HTML) 1 Page - ANADIGICS, Inc |
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1 / 25 page  March 2001 Copyright © Alliance Semiconductor. All rights reserved. ® AS29LV800 3V 1M × 8/512K × 16 CMOS Flash EEPROM 3/22/01; V.1.0 Alliance Semiconductor P. 1 of 25 Features • Organization: 1M×8/512K×16 • Sector architecture - One 16K; two 8K; one 32K; and fifteen 64K byte sectors - One 8K; two 4K; one 16K; and fifteen 32K word sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 2.7-3.6V power supply for read/write operations • Sector protection • High speed 70/80/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors • Hardware RESET pin - Resets internal state machine to read mode • Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current • JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO; availability TBD • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - DQ2 toggle bit -RY/BY output • Erase suspend/resume - Supports reading data from or programming data to a sector not being erased •Low VCC write lock-out below 1.5V • 10 year data retention at 150C • 100,000 write/erase cycle endurance Logic block diagram X decoder VCC VSS Cell matrix Y decoder Y gating Data latch Chip enable Input/output buffers Sector protect/ Command register Program/erase control VCC detector Erase voltage generator Program voltage generator Timer A0–A18 CE OE STB STB Output enable Logic RY/BY WE RESET DQ0–DQ15 switches erase voltage BYTE A-1 Pin arrangement 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 44-pin SO 21 22 DQ3 DQ11 A10 A11 A12 A13 2 A18 3 A17 4 A7 1 RY/BY 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 WE A8 A9 RESET 48-pin TSOP AS29LV800 Selection guide 29LV800-70R* * Regulated voltage range of 3.0 to 3.6V 29LV800-80 29LV800-90 29LV800-120 Unit Maximum access time tAA 70 80 90 120 ns Maximum chip enable access time tCE 70 80 90 120 ns Maximum output enable access time tOE 30 30 35 50 ns |
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