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AT91R40008

1732CS–ATARM–02/02

Remap Command

The ARM vectors (Reset, Abort, Data Abort, Pre-fetch Abort, Undefined Instruction, Interrupt,

Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors

to be redefined dynamically by the software, the AT91R40008 microcontroller uses a Remap

command that enables switching between the boot memory and the internal primary SRAM

bank addresses. The Remap command is accessible through the EBI User Interface by writing

one in RCB of EBI_RCR (Remap Control Register). Performing a Remap command is manda-

tory if access to the other external devices (connected to chip-selects 1 to 7) is required. The

Remap operation can only be changed back by an internal reset or an NRST assertion.

Abort Control

The abort signal providing a Data Abort or a Pre-fetch Abort exception to the ARM7TDMI is

asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal peripher-

als, whether or not the address is defined.

External Bus Interface

The External Bus Interface handles the accesses between addresses 0x0040 0000 and

0xFFC0 0000. It generates the signals that control access to the external devices, and can be

configured from eight 1M byte banks up to four 16M bytes banks. It supports byte-, half-word-

and word-aligned accesses.

For each of these banks, the user can program:

•

Number of wait states

•

Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

•

Data bus width (8-bit or 16-bit)

The user can program the EBI to control one 16-bit device (Byte Select Access mode) with a

16-bit wide data bus or two 8-bit devices in parallel that emulate a 16-bit memory (Byte Write

Access mode).

The External Bus Interface also features the Early Read Protocol, configurable for all the

devices, which significantly reduces access time requirements on an external device in the

case of single-clock cycle access.