8

AT89LS52

2601A–12/01

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data

Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1

selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before

accessing the respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power

up. It can be set and rest under software control and is not affected by reset.

Table 3. AUXR: Auxiliary Register

AUXR

Address = 8EH

Reset Value = XXX00XX0B

Not Bit Addressable

–

–

–

WDIDLE

DISRTO

–

–

DISALE

Bit

7

6

5

4

3

2

1

0

–

Reserved for future expansion

DISALE

Disable/Enable ALE

DISALE

Operating Mode

0

ALE is emitted at a constant rate of 1/6 the oscillator frequency

1

ALE is active only during a MOVX or MOVC instruction

DISRTO

Disable/Enable Reset out

DISRTO

0

Reset pin is driven High after WDT times out

1

Reset pin is input only

WDIDLE

Disable/Enable WDT in IDLE mode

WDIDLE

0

WDT continues to count in IDLE mode

1

WDT halts counting in IDLE mode

Table 4. AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Reset Value = XXXXXXX0B

Not Bit Addressable

––

–

–

–

–

–

DPS

Bit

7

6

5

4

3

2

1

0

–

Reserved for future expansion

DPS

Data Pointer Register Select

DPS

0

Selects DPTR Registers DP0L, DP0H

1

Selects DPTR Registers DP1L, DP1H