© Semiconductor Components Industries, LLC, 2014

July, 2014 − Rev. 11

1

Publication Order Number:

MC14012B/D

MC14012B

Dual 4-Input NAND Gates

The MC14012B dual 4−input NAND gates are constructed with

P−Channel and N−Channel enhancement mode devices in a single

monolithic structure (Complementary MOS). Their primary use is

where low power dissipation and/or high noise immunity is desired.

Features

Schottky TTL Load Over the Rated Temperature Range

Suffix Devices

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

− 0.5 to +18.0

V

Input or Output Voltage Range

(DC or Transient)

V

Input or Output Current

(DC or Transient) per Pin

±10

mA

Power Dissipation, per Package

(Note 1)

500

mW

Ambient Temperature Range

− 55 to +125

°C

Storage Temperature Range

− 65 to +150

°C

Lead Temperature

(8−Second Soldering)

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Package: –7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

Unused inputs must always be tied to an appropriate logic voltage level

MARKING DIAGRAM

SOIC−14

D SUFFIX

CASE 751A

1

14

14012BG

AWLYWW

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G

= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

http://onsemi.com