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LDC2112YFDT Datasheet(PDF) 7 Page - Texas Instruments |
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LDC2112YFDT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 49 page  SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF 7 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 6.6 Digital Interface Over operating free-air temperature range (unless otherwise noted). VDD = 1.8 V, TA = 25 °C. Pins: LPWRB, INTB, OUT0, OUT1, OUT2, and OUT3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE LEVELS VIH Input high voltage 0.8 × VDD V VIL Input low voltage 0.2 × VDD V VOH Output high voltage ISOURCE = 400 µA 0.7 × VDD V VOL Output low voltage ISINK = 400 µA 0.3 × VDD V IL Digital input leakage current –500 500 nA (1) This parameter is specified by design and/or characterization and is not tested in production. 6.7 I 2C Interface MIN TYP MAX UNIT VOLTAGE LEVELS VIH Input high voltage 0.7 × VDD V VIL Input low voltage 0.3 × VDD V VOL Output low voltage 2-mA sink current 0.2 × VDD V HYS Hysteresis(1) 0.05 × VDD V I2C TIMING CHARACTERISTICS fSCL Clock frequency 400 kHz tLOW Clock low time 1.3 µs tHIGH Clock high time 0.6 µs tHD;STA Hold time repeated START condition After this period, the first clock pulse is generated 0.6 µs tSU;STA Set-up time for a repeated START condition 0.6 µs tHD;DAT Data hold time 0 µs tSU;DAT Data set-up time 100 µs tSU;STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs tSP Pulse width of spikes that must be suppressed by the input filter(1) 50 ns Figure 1. I2C Timing Diagram |
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