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MLX81205 Datasheet(PDF) 7 Page - Melexis Microelectronic Systems |
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MLX81205 Datasheet(HTML) 7 Page - Melexis Microelectronic Systems |
7 / 18 page MLX81205/07 390108120502 Page 7 of 18 Product Abstract Rev. 4.7 11/2/2015 4. Electrical Characteristics All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings given in table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Reliable operation of the MLX81205/07 is only specified within the limits shown in Table 4. 4.1 Operating Conditions Parameter Symbol min max Unit IC supply voltage VS 5.0 18 V Operating ambient temperature Tamb -40 +125 (+150) 2 °C Table 4 – Operating Conditions 4.2 Absolute Maximum Ratings Parameter Symbol Condition min max Unit IC supply voltage on pins VS, VBAT_S1, VBAT_S2 VS T = 2 min -0.3 28 V T < 500 ms 3 45 VS.tr1 ISO 7637-2 pulse 1 4 VS=13.5V, TA=(23 ± 5)°C -100 V VS.tr2 ISO 7637-2 pulse 2 4 VS=13.5V, TA=(23 ± 5)°C +75 V VS.tr3 ISO 7637-2 pulses 3A, 3B 4 VS=13.5V, TA=(23 ± 5)°C -150 +100 V VS.tr5 ISO 7637-2 pulses 5b 4 VS=13.5V, TA=(23 ± 5)°C +65 +87 V LIN Bus VLIN T<500ms -25 40 V VLIN.tr1 ISO 7637-2 pulse 1 5 VS=13.5V, TA=(23 ± 5)°C -100 VLIN.tr2 ISO 7637-2 pulse 2 5 VS=13.5V, TA=(23 ± 5)°C +75 VLIN.tr3 ISO 7637-2 pulses 3A, 3B 6 VS=13.5V, TA=(23 ± 5)°C -150 +100 Maximum reverse current into any pin 7 -10 +10 mA Maximum sum of reverse currents into all pins 7 +10 mA DC voltage on LVIO pins, OSC<2:1> -0.3 VDDA+0.3 V DC voltage on pins HV I/O -0.3 VS+0.3 V 2 With temperature applications at TA>125°C a reduction of chip internal power dissipation by using an external supply transistor is mandatory. The extended temperature range is only allowed for a limited period of time, a mission profile has to be agreed by Melexis as a mandatory part of the Part Submission Warrant (PSW) 3 Only allowed, if FET drivers are disabled, i.e. the high-side driver must not be stressed with V(CP) > 45V 4 ISO 7637 test pulses are applied to VS via a reverse polarity diode and >22μF blocking capacitor 5 ISO 7637 test pulses are applied to LIN via a coupling capacitance of 1nF 6 ISO 7637 test pulses are applied to LIN via a coupling capacitance of 100pF 7 Excluding pins HS0, HS1, HS2, U, V, W, LS0, LS1, LS2. |
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