Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. E

11/26/03

IS62C1024L

WRITE CYCLE NO. 2 (

CE1

CE1

CE1

CE1

Notes:

1. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

AC WAVEFORMS

WRITE CYCLE NO. 1 (

WE

WE

WE

WE

DATA-IN VALID

DATA UNDEFINED

HIGH-Z

ADDRESS

CE1

CE2

WE

DOUT

DIN

HIGH-Z

DATA UNDEFINED

DATA-IN VALID

ADDRESS

DIN

CE1

CE2

WE

DOUT