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MC74HC373ADTR2G Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74HC373ADTR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 15 1 Publication Order Number: MC74HC373A/D MC74HC373A Octal 3-State Non-Inverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high−impedance state. Thus, data may be latched even when the outputs are not enabled. The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC373A is the non−inverting version of the HC533A. Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the JEDEC Standard No. 7.0 A Requirements • Chip Complexity: 186 FETs or 46.5 Equivalent Gates • These Devices are Pb−Free and are RoHS Compliant DATA INPUTS D0 D1 D2 D3 D4 D5 D6 D7 18 17 14 13 8 7 4 3 1 OUTPUT ENABLE 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16 15 12 9 6 5 2 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS 11 LATCH ENABLE LOGIC DIAGRAM http://onsemi.com MARKING DIAGRAMS See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION 1 20 SOIC−20 HC373A AWLYYWWG HC 373A ALYW G G TSSOP−20 20 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) SOIC−20 DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E FUNCTION TABLE Inputs Output Output Latch Enable Enable D Q LH H H LH L L L L X No Change HX X Z X = Don’t Care Z = High Impedance PIN ASSIGNMENT Q2 D1 D0 Q0 OUTPUT ENABLE GND Q3 D3 D2 Q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 Q6 D6 D7 Q7 VCC LATCH ENABLE Q4 D4 D5 Q5 |
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