 2016 Microchip Technology Inc.

DS20005583A-page 9

HV9912

voltage is between the start and stop voltages.

Therefore, it is recommended that the input voltage be

3.4

Reference

HV9912 includes a 2% accurate 1.25V reference,

which can be used as the reference for the output

current as well as to set the switch current limit. The

reference is buffered so that it can deliver a maximum

of 500 µA external current to drive the external circuitry.

The reference should be bypassed with at least a 10 nF

low-ESR capacitor.

Note:

To avoid abnormal Startup conditions, the

bypass capacitor at the REF pin should

not exceed 0.1 µF.

3.5

Oscillator

program the time period.

charges an internal oscillator capacitor. The capacitor

voltage ramps up linearly. When the voltage increases

beyond the internal set voltage, a comparator triggers

the set input of the internal SR flip-flop. This starts the

next switching cycle. The time period of the oscillator

can be computed as shown in Equation 3-4.

EQUATION 3-4:





3.6

Synchronization

The SYNC pin is an input/output (I/O) port to a

fault-tolerant

peer-to-peer

and/or

master

clock

synchronization circuit. For synchronization, the SYNC

pins of multiple HV9912-based converters can be

connected together and may also be connected to the

open drain output of a master clock. When connected

in this manner, the oscillators will lock to the device with

the highest operating frequency. When synchronizing

multiple ICs, it is recommended that the same timing

resistor (corresponding to the switching frequency) be

used in all the HV9912 circuits.

On rare occasions, given the length of the connecting

lines for the SYNC pins, a resistor between SYNC and

GND may be required to damp any ringing due to

parasitic capacitances. It is recommended that the

resistor chosen be greater than 300 kΩ.

When synchronized in this manner, a permanent High

or Low condition on the SYNC pin will result in a loss of

synchronization, but the HV9912-based converters will

continue to operate at their individually set operating

frequencies. Since loss of synchronization will not

result in total system failure, the SYNC pin is

considered fault tolerant.

3.7

Slope Compensation

For Continuous Conduction mode converters operating

in the Constant Frequency mode, slope compensation

becomes necessary to ensure stability of the Peak

Current mode controller if the operating duty cycle is

greater than 50%. Choosing a slope compensation

which is one half of the down slope of the inductor

current ensures that the converter will be stable for all

duty cycles.

Slope compensation can be programmed by two

DS (A/µs) for the inductor current, the slope

compensation resistors can be computed as illustrated

in Equation 3-5.

EQUATION 3-5:

6









10

--------------------------------------------------------------------------

=

senses the switching FET current

Note:

The maximum current that can be sourced

out of the SC pin is 100 µA. This limits the

25 kΩ. If the equation for slope

reduced accordingly. It is recommended

25 kΩ to 50 kΩ.

3.8

Current Sense

The current sense input of the HV9912 includes a

built-in 100 ns (minimum) blanking time to prevent

spurious turn-off due to the initial current spike when

the FET turns on.

The HV9912 includes two high-speed comparators—

one is used during normal operation and the other is

used to limit the maximum input current during Input

Undervoltage or Overload conditions.

The IC includes an internal resistor divider network,

which steps down the voltage at the COMP pin by a

factor of 15. This stepped-down voltage is given to one

of the comparators as the current reference. The

reference to the other comparator, which acts to limit

the maximum inductor current, is given externally.

chosen so as to provide about 250 mV current sense

signal.