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LAN8740A-EN-TR Datasheet(PDF) 4 Page - Microchip Technology |
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LAN8740A-EN-TR Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 136 page  LAN8740A/LAN8740Ai DS00001987A-page 4 2013-2015 Microchip Technology Inc. 1.0 INTRODUCTION 1.1 General Terms and Conventions The following is a list of the general terms used throughout this document: 1.2 General Description The LAN8740A/LAN8740Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O voltage that is compliant with the IEEE 802.3, 802.3u, and 802.3az (Energy Efficient Ethernet) standards. Energy Effi- cient Ethernet (EEE) support results in significant power savings during low link utilizations. The LAN8740A/LAN8740Ai supports communication with an Ethernet MAC via a standard MII (IEEE 802.3u)/RMII inter- face. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10 Mbps (10BASE-T) and 100 Mbps (100BASE-TX) operation. The LAN8740A/LAN8740Ai implements auto-negotiation to automatically determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over LAN cables. Integrated Wake on LAN (WoL) support provides a mechanism to trigger an interrupt upon reception of a perfect DA, broadcast, magic packet, or wakeup frame. The LAN8740A/LAN8740Ai supports both IEEE 802.3-2005 compliant and vendor-specific register functions. However, no register access is required for operation. The initial configuration may be selected via the configuration pins as described in Section 3.7, "Configuration Straps". Register-selectable configuration options may be used to further define the functionality of the transceiver. The LAN8740A/LAN8740Ai can be programmed to support wake-on-LAN at the physical layer, allowing detection of configurable Wake-up Frame and Magic packets. This feature allows filtering of packets at the PHY layer, without requir- ing MAC intervention. Additionally, the LAN8740A/LAN8740Ai supports cable diagnostics which allow the device to identify opens/shorts and their location on the cable via vendor-specific registers. Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6 V. The device can be configured to operate on a single 3.3 V supply utilizing an integrated 3.3 V to 1.2 V linear regulator. The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation. BYTE 8 bits FIFO First In First Out buffer; often used for elasticity buffer MAC Media Access Controller MII Media Independent Interface RMII™ Reduced Media Independent Interface N/A Not Applicable X Indicates that a logic state is “don’t care” or undefined. RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. SMI Serial Management Interface |
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