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BU9408KS2 Datasheet(PDF) 9 Page - Rohm

Part # BU9408KS2
Description  32bit Audio DSP with Built-in 4ch DAC and ASRC
Download  57 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU9408KS2 Datasheet(HTML) 9 Page - Rohm

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Technical Note
9/53
BU9408KS2
www.rohm.com
2012.03 - Rev.A
© 2012 ROHM Co., Ltd. All rights reserved.
1
1--3
3..
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all S
Sp
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ciiffiic
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attiio
on
ns
s
Electrical Characteristics and Timing for Bus Line and I/O Stage
Fig.1-1: Timing Chart
Table 1-1: SDA and SCL Bus Line Characteristics
(Ta=25℃ and VDD=3.3V)
Parameters
Symbol
High-Speed Mode
Unit
Min.
Max.
1
SCL clock frequency
fSCL
0
400
kHz
2
Bus free time between “stop” condition and
“start” condition
tBUF
1.3
μS
3
Hold time (re-transmit) “start” condition.
After this period, the first clock pulse is generated.
tHD;STA
0.6
μS
4
SCL clock LOW state hold time
tLOW
1.3
μS
5
SCL clock HIGH state hold time
tHIGH
0.6
μS
6
Re-transmit set-up time of “start” condition
tSU;STA
0.6
μS
7
Data hold time
tHD;DAT
0
1)
μS
8
Data setup time
tSU;DAT
100
ns
9
SDA and SCL signal stand-up time
tR
20+Cb
300
ns
10
SDA and SCL signal stand-down time
tF
20+Cb
300
ns
11
Set-up time for “stop” condition
tSU;STO
0.6
μS
12
Each bus line’s capacitive load
Cb
400
pF
The values above correspond with VIH min and VIL max levels.
1)
Because the transmission device exceeds the undefined domain of the SCL fall edge, it is necessary to
internally provide a minimum 300ns
hold time for the SDA signal (of VIH min of SCL signal).
The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.
When problem occurs by any chance, we talk in good faith and correspond.
Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V.
tBUF
tLOW
tR
tHD;STA
S
P
tHD;DAT
tF
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
P
SDA
SCL


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