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HI8455PSTF Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI8455PSTF Datasheet(HTML) 2 Page - Holt Integrated Circuits |
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2 / 11 page  HI-8450, HI-8451, HI-8454, HI-8455 HOLT INTEGRATED CIRCUITS 2 BLOCK DIAGRAMS TEST RINA RINB NULL ZERO NULL ONE TESTA ROUTB ROUTA SQ R LATCH LATCH SQ TESTB R TESTA TESTB TEST LIGHTNING PROTECTION AND TRANSLATION Figure 1. Line Receiver Block Diagram IN1A IN1B IN2A IN2B IN3A IN3B IN4A IN4B TESTA TESTB OUT1A OUT1B OUT2A OUT3A OUT3B OUT4A OUT4B OUT2B Figure 2. HI-8454 Block Diagram FUNCTIONAL DESCRIPTION Figure 1 shows the general architecture of an ARINC 429 receiver. The receiver operates off the VDD supply only. The inputs RINA and RINB may be connected directly to the ARINC 429 bus. Internal lightning protection circuitry ensures compliance with RTCA/DO-160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B) without the use of any external components. After level translation, the inputs are buffered and becomeinputstoadifferentialamplifier.Theamplitude of the differential signal is compared to levels derived from a divider between VDD and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins (not available on HI-8455). If TESTA and TESTB are both One, the outputs are pulled low (HI- 8451 and HI-8454 only). This allows the digital outputs of a transmitter to be connected to the test inputs through control logic for system self-test purposes. In the case of HI-8450, if TESTA and TESTB are both One, the outputs are high impedance (HI-Z). |
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