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PL611S-02 Datasheet(PDF) 9 Page - Microchip Technology |
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PL611S-02 Datasheet(HTML) 9 Page - Microchip Technology |
9 / 20 page 2016 Microchip Technology Inc. DS20005670A-page 9 PL611S-02 4.0 LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design. 4.1 Signal Integrity and Termination Considerations • Keep traces short! • Trace = Inductor. With a capacitive load this equals ringing • Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). • Design long traces (greater than one inch) as striplines or microstrips with defined impedance. • Match trace at one side to avoid reflections bouncing back and forth. 4.2 Decoupling and Power Supply Considerations • Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply • Multiple VDD pins should be decoupled separately for best performance. • Addition of a ferrite bead in series with VDD can help prevent noise from other board sources • Value of decoupling capacitor is frequency dependent. Typical values to use are 0.1 μF for designs using frequencies < 50 MHz and 0.01 μF for designs using frequencies > 50 MHz. FIGURE 4-1: Typical CMOS Termination. FIGURE 4-2: Crystal Tuning Circuit. Typical CMOS Termination Place Series Resistor as close as possible to CMOS output. CMOS Output Buffer (Typical buffer impedance 20Ω) To CMOS Input Series Resistor Use value to match output buffer impedance to 50Ω trace. Typical value is 30Ω. 50Ω Line Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load. Crystal XIN 18 XOUT CPT CPT CST CST: Series Capacitor that is used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated by using a crystal with a C LOAD of equal or greater value than the oscillator. CPT: Parallel Capacitors that are used to raise the circuit load to match the crystal load. Lowers frequency offset. |
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