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BLUENRG-132Y Datasheet(PDF) 7 Page - STMicroelectronics |
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BLUENRG-132Y Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 173 page BlueNRG-1 List of tables DocID028866 Rev 1 7/173 Table 96: I2C - SR register description: address offset I2CX_BASE_ADDR+0x14 .................................89 Table 97: I2C - RFR register description: address offset I2CX_BASE_ADDR+0x18 ..............................91 Table 98: I2C - TFTR register description: address offset I2CX_BASE_ADDR+0x1C ............................91 Table 99: I2C - RFTR register description: address offset I2CX_BASE_ADDR+0x20 ............................91 Table 100: I2C - DMAR register description: address offset I2CX_BASE_ADDR+0x24 .........................91 Table 101: I2C - BRCR register description: address offset I2CX_BASE_ADDR+0x28..........................92 Table 102: I2C - IMSCR register description: address offset I2CX_BASE_ADDR+0x2C .......................92 Table 103: I2C - RISR register description: address offset I2CX_BASE_ADDR+0x30. ..........................94 Table 104: I2C - MISR register description: address offset I2CX_BASE_ADDR+0x34...........................97 Table 105: I2C - ICR register description: address offset I2CX_BASE_ADDR+0x38..............................99 Table 106: I2C - THDDAT register description: address offset I2CX_BASE_ADDR+0x4C ..................100 Table 107: I2C - THDSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x50 .100 Table 108: I2C - TSUSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x58 .100 Table 109: Flash commands ..................................................................................................................104 Table 110: Flash interface timing............................................................................................................104 Table 111: FLASH controller registers....................................................................................................104 Table 112: FLASH – COMMAND register description: address offset FLASH_BASE_ADDR+0x00 ....105 Table 113: FLASH – CONFIG register description: address offset FLASH_BASE_ADDR+0x04 .........105 Table 114: FLASH - IRQSTAT register description: address offset FLASH_BASE_ADDR+0x08 ........105 Table 115: FLASH - IRQMASK register description: address offset FLASH_BASE_ADDR+0x0C .......106 Table 116: FLASH - IRQRAW register description: address offset FLASH_BASE_ADDR+0x10 .........106 Table 117: FLASH – SIZE register description: address offset FLASH_BASE_ADDR+0x14 ...............106 Table 118: FLASH – ADDRESS register description: address offset FLASH_BASE_ADDR+0x18 ......106 Table 119: FLASH – LFSRVAL register description: address offset FLASH_BASE_ADDR+0x24 .......106 Table 120: FLASH – TIMETRIM1 register description: address offset FLASH_BASE_ADDR+0x28....106 Table 121: FLASH – TIMETRIM2 register description: address offset FLASH_BASE_ADDR+0x2C ...107 Table 122: FLASH – TIMETRIM3 register description: address offset FLASH_BASE_ADDR+0x30 ....107 Table 123: FLASH – DATA0 register description: address offset FLASH_BASE_ADDR+0x40............107 Table 124: FLASH – DATA1 register description: address offset FLASH_BASE_ADDR+0x44............107 Table 125: FLASH – DATA2 register description: address offset FLASH_BASE_ADDR+0x48............107 Table 126: FLASH – DATA3 register description: address offset FLASH_BASE_ADDR+0x4C ...........107 Table 127: IO functional map..................................................................................................................108 Table 128: GPIO interrupt modes...........................................................................................................109 Table 129: Pin characteristics.................................................................................................................109 Table 130: IO pull values ........................................................................................................................109 Table 131: GPIO registers ......................................................................................................................111 Table 132: GPIO – DATA register description: address offset GPIO_BASE_ADDR+0x00 ...................112 Table 133: GPIO – OEN register description: address offset GPIO_BASE_ADDR+0x04.....................112 Table 134: GPIO – PE register description: address offset GPIO_BASE_ADDR+0x08........................112 Table 135: GPIO – DS register description: address offset GPIO_BASE_ADDR+0x0C .......................112 Table 136: GPIO – IS register description: address offset GPIO_BASE_ADDR+0x10 .........................113 Table 137: GPIO – IBE register description: address offset GPIO_BASE_ADDR+0x14.......................113 Table 138: GPIO – IEV register description: address offset GPIO_BASE_ADDR+0x18.......................113 Table 139: GPIO – IE register description: address offset GPIO_BASE_ADDR+0x1C.........................113 Table 140: GPIO – MIS register description: address offset GPIO_BASE_ADDR+0x24 ......................113 Table 141: GPIO – IC register description: address offset GPIO_BASE_ADDR+0x28 .........................113 Table 142: GPIO - MODE0 register description: address offset GPIO_BASE_ADDR+0x2C ................113 Table 143: GPIO – MODE1 register description: address offset GPIO_BASE_ADDR+0x30................114 Table 144: GPIO – DATS register description: address offset GPIO_BASE_ADDR+0x3C ..................114 Table 145: GPIO – DATC register description: address offset GPIO_BASE_ADDR+0x40...................115 Table 146: GPIO - MFTX register description: address offset GPIO_BASE_ADDR+0x44....................115 Table 147: MFT modes...........................................................................................................................116 Table 148: MFT IO functions ..................................................................................................................124 Table 149: MFT interrupt functions .........................................................................................................125 Table 150: MFTX registers .....................................................................................................................126 Table 151: MFTX – TNCNT1 register description: address offset MFTX_BASE_ADDR+0x00.............126 |
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