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5962-9561316HYC Datasheet(PDF) 1 Page - Micross Components |
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5962-9561316HYC Datasheet(HTML) 1 Page - Micross Components |
1 / 12 page SRAM AS5C4009 AS5C4009 Rev. 5.2 01/10 Micross Components reserves the right to change products or specifications without notice. 1 AVAILABLE AS MILITARY SPECIFICATION • SMD 5962-956131,2 • MIL STD-8831 FEATURES • Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) • Fully Static, No Clocks • Single +5V ±10% power supply • Easy memory expansion with CE\ and OE\ options • All inputs and outputs are TTL-compatible • Three state outputs • Operating temperature range: Ceramic -55oC to +125oC & -40oC to +85oC Plastic -40oC to +85oC3 1. Not applicable to plastic package 2. Applies to CW package only. 3. Contact factory for -55oC to +125oC OPTIONS MARKING • Timing 55ns access -554 70ns access -70 85ns access -85 100ns access -100 • Packages Ceramic Dip (600 mil) CW No. 112 Ceramic SOJ5 ECJ No. 502 Plastic TSOP DG No. 1002 • Options 2V data retention/very low power L PIN ASSIGNMENT (Top View) 32-Pin DIP, 32-Pin SOJ & 32-Pin TSOP 4. For DG package, contact factory 5. Contact Factory NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combina- tions. 512K x 8 SRAM Ultra Low Power SRAM For more products and information please visit our web site at www.micross.com GENERAL DESCRIPTION The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. Micross’ pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. For flexibility in memory applications, Micross offers chip enable (CE\) and output enable (OE\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. This devices operates from a single +5V power supply and all inputs and outputs are fully TTL-compatible. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled, by lowering VCC to 2V and maintaining CE\ = 2V. This allows system designers to meet ultra low standby power requirements. Pin Name Function WE\ Write Enable Input CE\ Chip Select Input OE\ Output Enable Input A0 - A18 Address Inputs I/O1 - I/O8 Data Inputs/Outputs Vcc Power Vss Ground A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/01 I/02 I/03 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE\ A13 A8 A9 A11 OE\ A10 CE\ I/08 I/07 I/06 I/05 I/04 |
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