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AS4SD8M16 Datasheet(PDF) 2 Page - Micross Components |
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AS4SD8M16 Datasheet(HTML) 2 Page - Micross Components |
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2 / 52 page  SDRAM AS4SD8M16 AS4SD8M16 Rev. 1.6 March 27, 2015 Micross Components reserves the right to change products or specifications without notice. 2 GENERAL DESCRIPTION The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134, 217, 728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33, 554, 432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random operation. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V mem- ory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. FUNCTIONAL BLOCK DIAGRAM 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 10/19/2011 IS45S81600E, IS45S16800E DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. CLK CKE CS RAS CAS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A10 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQML DQMH DQ 0-15 VDD/VDDQ Vss/VssQ 12 12 9 12 12 9 16 16 16 16 512 (x 16) 4096 4096 4096 4096 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER A11 2 FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONlY) |
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