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PL138-48QC Datasheet(PDF) 1 Page - Microchip Technology |
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PL138-48QC Datasheet(HTML) 1 Page - Microchip Technology |
1 / 20 page 2016 Microchip Technology Inc. DS20005543B-page 1 PL138-48 Features • Four Differential 2.5V/3.3V LVPECL Output Pairs • Output Frequency: ≤800 MHz • Two Selectable Differential Input Pairs • Translates Any Standard Single-Ended or Differential Input Format to LVPECL Output. It Can Accept the Following Standard Input Formats and More: - LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML • Output Skew: 25 ps (typ.) • Part-to-Part Skew: 140 ps (typ.) • Propagation Delay: 1.5 ns (typ.) • Additive Jitter: <100 fs (max.) • Operating Supply Voltage: 2.375V ~ 3.63V • Operating Temperature Range from –40°C to +85°C • Package Availability: 16-Pin QFN and 20-Pin TSSOP General Description The PL138-48 is a high performance low-cost 1:4 outputs differential LVPECL fanout buffer. Microchip’s family of differential LVPECL buffers are designed to operate from a single power supply of 2.5V ±5% or 3.3V ±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to-lot skew. Designed to fit in a small form-factor package, the PL138-48 offers up to 800 MHz of output operation with very low-power consumption and lowest additive jitter of any comparable device. Block Diagram 2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer |
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