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LP5912Q3.3DRVTQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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LP5912Q3.3DRVTQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 33 page 4 LP5912-Q1 SNVSAA8C – DECEMBER 2015 – REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: LP5912-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the GND pin. (3) Internal thermal shutdown circuitry protects the device from permanent damage. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VIN Input voltage –0.3 7 V VOUT Output voltage –0.3 7 V VEN Enable input voltage –0.3 7 V VPG Power Good (PG) pin OFF voltage –0.3 7 V TJ Junction temperature 150 °C PD Continuous power dissipation(3) Internally Limited W Tstg Storage temperature –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±1000 (1) All voltages are with respect to the GND pin. (2) TJ-MAX-OP = (TA(MAX) + (PD(MAX) × RθJA )). 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN Input supply voltage 1.6 6.5 V VOUT Output voltage 0.8 5.5 V VEN Enable input voltage 0 VIN V VPG PG pin OFF voltage 0 6.5 V IOUT Output current 0 500 mA TJ-MAX-OP Operating junction temperature(2) –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. (3) The PCB for the WSON (DRV) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5. 7.4 Thermal Information THERMAL METRIC(1) LP5912-Q1 UNIT DRV (WSON) 6 PINS RθJA Junction-to-ambient thermal resistance, High-K(2) 71.2(3) °C/W RθJC(top) Junction-to-case (top) thermal resistance 93.7 °C/W RθJB Junction-to-board thermal resistance 40.7 °C/W ψJT Junction-to-top characterization parameter 2.5 °C/W ψJB Junction-to-board characterization parameter 41.1 °C/W ψJC(bot) Junction-to-case (bottom) thermal resistance 11.2 °C/W |
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