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ADS1113BQDGSRQ1 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1113BQDGSRQ1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 50 page  SCL SDA t LOW t R t F t HDSTA t HDSTA t HDDAT t BUF t SUDAT t HIGH t SUSTA t SUSTO P S S P 8 ADS1113-Q1, ADS1114-Q1, ADS1115-Q1 SBAS563C – DECEMBER 2011 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADS1113-Q1 ADS1114-Q1 ADS1115-Q1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Electrical Characteristics (continued) At VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted). Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY IVDD Supply current Power-down TA = 25°C 0.5 2 µA 5 Operating TA = 25°C 150 200 300 PD Power dissipation VDD = 5.0 V 0.9 mW VDD = 3.3 V 0.5 VDD = 2.0 V 0.3 (1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF. 7.6 Timing Requirements: I 2C over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted) FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX fSCL SCL clock frequency 0.01 0.4 0.01 3.4 MHz tBUF Bus free time between START and STOP condition 600 160 ns tHDSTA Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns tSUSTA Setup time for a repeated START condition 600 160 ns tSUSTO Setup time for STOP condition 600 160 ns tHDDAT Data hold time 0 0 ns tSUDAT Data setup time 100 10 ns tLOW Low period of the SCL clock pin 1300 160 ns tHIGH High period for the SCL clock pin 600 60 ns tF Rise time for both SDA and SCL signals(1) 300 160 ns tR Fall time for both SDA and SCL signals(1) 300 160 ns Figure 1. I2C Interface Timing |
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