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TMS320V642AGDK5 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320V642AGDK5 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 178 page  www.ti.com 1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 1.1 Features TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Memory Space • High-Performance Digital Media Processor – 2-, 1.67-, 1.39-ns Instruction Cycle Time • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) – 500-, 600-, 720-MHz Clock Rate – Eight 32-Bit Instructions/Cycle • 10/100 Mb/s Ethernet MAC (EMAC) – 4000, 4800, 5760 MIPS – IEEE 802.3 Compliant – Fully Software-Compatible With C64x™ – Media Independent Interface (MII) – 8 Independent Transmit (TX) Channels and • VelociTI.2™ Extensions to VelociTI™ 1 Receive (RX) Channel Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core • Management Data Input/Output (MDIO) – Eight Highly Independent Functional Units • Three Configurable Video Ports With VelociTI.2™ Extensions: – Providing a Glueless I/F to Common Video • Six ALUs (32-/40-Bit), Each Supports Decoder and Encoder Devices Single 32-Bit, Dual 16-Bit, or Quad 8-Bit – Supports Multiple Resolutions/Video Stds Arithmetic per Clock Cycle • VCXO Interpolated Control Port (VIC) • Two Multipliers Support Four 16 x 16-Bit – Supports Audio/Video Synchronization Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Host-Port Interface (HPI) [32-/16-Bit] Results) per Clock Cycle • 32-Bit/66-MHz, 3.3-V Peripheral Component – Load-Store Architecture With Non-Aligned Interconnect (PCI) Master/Slave Interface Support Conforms to PCI Specification 2.2 – 64 32-Bit General-Purpose Registers • Multichannel Audio Serial Port (McASP) – Instruction Packing Reduces Code Size – Eight Serial Data Pins – All Instructions Conditional – Wide Variety of I2S and Similar Bit Stream • Instruction Set Features Format – Byte-Addressable (8-/16-/32-/64-Bit Data) – Integrated Digital Audio I/F Transmitter – 8-Bit Overflow Protection Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats – Bit-Field Extract, Set, Clear • Inter-Integrated Circuit (I2C Bus™) – Normalization, Saturation, Bit-Counting – VelociTI.2™ Increased Orthogonality • Two Multichannel Buffered Serial Ports • L1/L2 Memory Architecture • Three 32-Bit General-Purpose Timers – 128K-Bit (16K-Byte) L1P Program Cache • Sixteen General-Purpose I/O (GPIO) Pins (Direct Mapped) • Flexible PLL Clock Generator – 128K-Bit (16K-Byte) L1D Data Cache (2-Way • IEEE-1149.1 (JTAG) Boundary- Set-Associative) Scan-Compatible – 2M-Bit (256K-Byte) L2 Unified Mapped • 548-Pin Ball Grid Array (BGA) Package RAM/Cache (Flexible RAM/Cache Allocation) (GDK and ZDK Suffixes), 0.8-mm Ball Pitch • Endianess: Little Endian, Big Endian • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch • 64-Bit External Memory Interface (EMIF) • 0.13-µm/6-Level Cu Metal Process (CMOS) – Glueless Interface to Asynchronous Memories (SRAM and EPROM) and • 3.3-V I/O, 1.2-V Internal (-500) Synchronous Memories (SDRAM, SBSRAM, • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, ZBT SRAM, and FIFO) -720) • 1024M-Byte Total Addressable External Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Windows is a registered trademark of Microsoft Corporation. I2C Bus is a trademark of Philips Electronics N.V.. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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