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V61184TAB Datasheet(PDF) 6 Page - EM Microelectronic - MARIN SA |
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V61184TAB Datasheet(HTML) 6 Page - EM Microelectronic - MARIN SA |
6 / 15 page R V6118 Pin Assignment Name Function S1..S40 LCD outputs, see Table 7 V3 LCD voltage bias level 3 (note 1, 2) V2 LCD voltage bias level 2 (note 1) V1 LCD voltage bias level 1 (note 1) VLCD Power supply for the LCD FR AC input signal for LCD driver output DI Serial data input DO Serial data output CLK Data clock input STR Data strobe, blank, synchronize input VDD Power supply for logic COL Column only driver mode VSS Supply GND Table 9 Note 1 : The V6118 has internal voltage bias level generation. When driving large pixels, an external resistor divider chain can be connected to the voltage bias level inputs to obtain enhanced display contrast (see Fig. 12, 13 and 14). The external resistor divider ratio should be in accordance with the internal resistor ratio (see Table 8). Note 2 : V3 is connected internally on the V6118 4. Name COL inactive COL active V6118 (2) V6118 (4) V6118 (8) S1 Row1 Row1 Row1 Col1 S2 Row2 Row2 Row2 Col2 S3 Col1 Row3 Row3 Col3 S4 Col2 Row4 Row4 Col4 S5 Col3 Col1 Row5 Col5 S6 Col4 Col2 Row6 Col6 S7 Col5 Col3 Row7 Col7 S8 Col6 Col4 Row8 Col8 S9…S40 Col7…38 Col5…36 Col1…32 Col9…40 Table 7 LCD Voltage Bias Levels LCD Drive Type LCD Bias Configuration ) rms ( V V OFF OP (note 1) ) rms ( V ) rms ( V OFF ON V6118 (2) n=2 1:2 MUX Alt + Pleshko 5 levels 3.69 n 1 1 2n = − 2.41 1 n 1 n = − + V6118 (4) n=4 1:4 MUX 1/3 Bias 4 Levels 3 1.73 n 8 1 = + V6118 (8) n=8 1:8 MUX 1/4 Bias 5 Levels 3.4 n 3 1 4 = + 1.446 3 n 15 n = + + Table 8 Note 1 : VOP = VLCD - VSS Copyright © 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com |
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