S-24C256C

10

3. Data transmission

Changing the SDA line while the SCL line is low, data is transmitted.

Changing the SDA line while the SCL line is high, a start or stop condition is recognized.

SCL

SDA

Figure 9 Data Transmission Timing

4. Acknowledge

The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA

line to acknowledge the receipt of the 8-bit data.

When an internal write cycle is in progress, the S-24C256C does not generate an acknowledge.

1

8

9

Acknowledge

Output

Start Condition

SCL

(E

SDA

(Master Output)

SDA

(E

Figure 10 Acknowledge Output Timing