2

©2016 Integrated Device Technology, Inc.

Revison B, February 8, 2016

850S1201 Datasheet

Pin Description and Pin Characteristics

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1

CLK8

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

2

CLK9

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

3

CLK10

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

4

CLK11

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

Power

Power supply pin.

6,

7.

8,

9

CLK_SEL0,

CLK_SEL1,

CLK_SEL2,

CLK_SEL3

Input

Pulldown

Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.

10

OE

Input

Pullup

Output enable pin for Q output. LVCMOS/LVTTL interface levels.

11

Q

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

12

GND

Power

Power supply ground.

13

CLK0

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

14

CLK1

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

15

CLK2

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

16

CLK3

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

17

CLK4

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

18

CLK5

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

19

CLK6

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

20

CLK7

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

2pF

Power Dissipation Capacitance

10

pF

8

pF

Input Pullup Resistor

51

k



51

k



Output Impedance

20



25

