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NVL74HC240ADWG Datasheet(PDF) 1 Page - ON Semiconductor

Part # NVL74HC240ADWG
Description  Octal 3-State Inverting Buffer/Line Driver/Line Receiver
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NVL74HC240ADWG Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 13
1
Publication Order Number:
MC74HC240A/D
MC74HC240A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
The MC74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3−state memory address drivers, clock drivers, and
other sub−oriented systems. The device has inverting outputs and two
active−low output enables.
The HC240A is similar in function to the HC244A.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 120 FETs or 30 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
NPUTS
A1
A2
A3
A4
B1
B2
B3
B4
17
15
13
11
8
6
4
218
16
14
12
9
7
5
3
YB4
YB3
YB2
YB1
YA4
YA3
YA2
YA1
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
OUTPUT
ENABLES
ENABLE A
ENABLE B
1
19
http://onsemi.com
1
20
MARKING DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
HC240A
AWLYYWWG
HC
240A
ALYW
G
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20
TSSOP−20
PIN ASSIGNMENT
A3
A2
YB4
A1
ENABLE A
GND
YB1
A4
YB2
YB3
5
4
3
2
1
10
9
8
7
6
YA2
B4
YA1
ENABLE B
VCC
B1
YA4
B2
YA3
B3
16
17
18
19
20
11
12
13
14
15
FUNCTION TABLE
Inputs
Outputs
Enable A,
Enable B
A, B
YA, YB
LL
H
LH
L
HX
Z
Z = high impedance


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