4 / 9 page
CY7C128A
4
Switching Waveforms
Read Cycle No. 1[10,11]
Read Cycle No. 2[10,12]
Write Cycle No. 1 (WE Controlled)[9,13]
Notes:
10. WE is HIGH for read cycle.
11.
Device is continuously selected. OE, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
ADDRESS
C128A–6
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
C128A–7
VCC
SUPPLY
CURRENT
tWC
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZWE
tLZWE
tSD
C128A–8
CE
WE
DATA IN
DATA I/O
ADDRESS
DATAIN VALID
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
