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DSP56F805D Datasheet(PDF) 10 Page - Motorola, Inc |
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DSP56F805D Datasheet(HTML) 10 Page - Motorola, Inc |
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10 / 48 page  10 56F805 Technical Data 2.5 Interrupt and Program Control Signals Table 9. Bus Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 1 PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory access. 1 DS Output Tri-stated Data Memory Select—DS is asserted low for external Data memory access. 1 WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles. When WR is asserted low, pins D0–D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. 1 RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the device’s data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0– A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Table 10. Interrupt and Program Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 1 IRQA Input (Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative- edge-triggered. 1 IRQB Input (Schmitt) Input External Interrupt Request B—The IRQB input is an external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. 1 RESET Input (Schmitt) Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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