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8413S12B Datasheet(PDF) 2 Page - Integrated Device Technology |
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8413S12B Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 33 page  2 ©2016 Integrated Device Technology, Inc Revision E, August 18, 2016 8413S12B Datasheet. Block Diagram QA0, nQA0 QF 50MHz QA1, nQA1 Clock Output Control Logic FSEL_A [0:1] QREF0 00 = 100MHz 01 = 125MHz 10 = 156.25MHz 11 = 312.5MHz QB0, nQB0 QB1, nQB1 QREF1 QG 125MHz OE_REF FSEL_B [0:1] FSEL_C [0:1] FSEL_D [0:1] QC0, nQC0 QC1, nQC1 QD0, nQD0 QD1, nQD1 OSC 00 = 100MHz 01 = 125MHz 10 = 156.25MHz 11 = 312.5MHz 00 = 100MHz 01 = 125MHz 10 = 156.25MHz 11 = 312.5MHz 00 = 100MHz 01 = 125MHz 10 = 156.25MHz 11 = 312.5MHz 00 = 100MHz 01 = 125MHz 10 = 156.25MHz 11 = 312.5MHz 0 1 FSEL_E [0:1] 0 1 CLK, nCLK QE0, nQE0 QE1, nQE1 nMR PLL_SEL REF_SEL OE_G OE_E OE_D OE_C OE_B OE_A XTAL_IN XTAL_OUT IREF 2 2 2 2 2 VCO Pullup Pulldown Pullup/ Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Pullup NOTE: OE_[A:G] and OE_REF pins have pullup resistors. |
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