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MIL-STD-1553B Datasheet(PDF) 10 Page - Aeroflex Circuit Technology |
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MIL-STD-1553B Datasheet(HTML) 10 Page - Aeroflex Circuit Technology |
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10 / 14 page  10 SCDCT1775 Rev B 21 DEC RST 20 -0.4 A LOW on this input (1 µsec minimum) resets the decoderto its initialized state, resets COMM/DATA SYNC to a LOW, and resets VALID WORD to a HIGH. 22 DSC OUT -0.4 4.0 LOW to HIGH transitions on this output when TAKE DATA is LOW causes causes receive cycle data shifting to occur. 23 SEND DATA -0.4 4.0 A HIGH on this output indicates that transmit cycle data shifting is occuring. 24 CLOCK IN ±1 ±.001 12 MHz clock input (20pF load) (see text). 25 S/T SELECT 20 -0.4 A HIGH on this input enables offline wraparound selftest.The transceiver is disabled and the encoder output is connected to the decoder input (see text). 26 FAIL-SAFE -0.4 4.0 A HIGH on this output indicates that a transmitted message has exceeded 768 µsec, and that transmission has been terminated. FAIL-SAFE is reset by either FIT ENABLE or MRST. 27 RT ENABLE -0.4 4.0 A HIGH on this output indicates receipt of a valid COMMAND word containing the correct 5 bit terminal address plus address parity. FAIL-SAFE is reset when FIT ENABLE goes HIGH. 28 MODE CODE -0.4 4.0 A LOW on this output indicates the reception of a valid COMMAND word whose sub-address field contains all ONES or all ZEROES. 29 LATCH DATA 2 20 -0.4 A HIGH on this input causes parallel tri-state I/O data on D0 through D7 to appear at the output of the first rank transmit register. A LOW locks out the register inputs. 30 ENCENABLE 20 -0.4 A LOW on this input causes the transmit cycle to start at the next HIGH to LOW transition of ESC OUT 31 BROADCAST -0.4 4.0 A HIGH on this output indicates reception of a valid COMMAND word whose address field contains all ONES, if BDCST INH is HIGH. 32 TMADD0* 20 -0.4 LSB of 5-bit hard-wired terminal address input. 33 TMADD2* 20 -0.4 Part of 5-bit hard-wired terminal address input. 34 TMADD4* 20 -0.4 MSB of 5-bit hard-wired terminal address input. 35 TMADDP 20 -0.4 Parity bit of hard-wired terminal address. Hard-wired for odd parity. 36 CHAN SELECT 100 -2.0 A LOW on this input enables DATA SELECT 1, DATA SELECT 2, LATCH DATA 1, LATCH DATA 2, and ENC ENABLE inputs. 37 ODD PARITY -0.36 3.6 A HIGH on this output indicates a valid check for odd parity of terminal address plus parity bits, if ENA PAR CHECK is a LOW. 38 D15 20 -0.2 -12 12 MSB of 16 bit parallel tri-state I/O. PIN FUNCTION AND LOADING TABLE (con’t) PIN # NAME IIH (µA) IIL (mA) IOH (mA) IOL (mA) DESCRIPTION |
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