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1775 Datasheet(PDF) 4 Page - Aeroflex Circuit Technology

Part # 1775
Description  Universal MacAir/1553 Dumb RTU Hybrid PRELIMINARY DATA SHEET
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

1775 Datasheet(HTML) 4 Page - Aeroflex Circuit Technology

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SCDCT1775 Rev B
GENERAL
As shown in the block diagram of Figure 1, the CT1775
provides all functions required to implement a Dumb Remote
Terminal Unit (RTU). It is designed for the greatest flexibility
and ease of use. CT1775 can be operated with either an
internal or external clock. Simple control lines are provided to
interface with either single channel or dual redundant
configurations.
Control lines are available to implement either on line or off
line wraparound built-in test. CT1775 can be configured to
perform a parity check on its hard-wired terminal address. It
provides numerous output flags to simplify the use interface.
These flags indicate various decoded messages, as well as the
results of error checks. Sync selection, along with the flexible
controls, allows the CT1775 to operate as a Bus Controller as
well as a Remote Terminal.
INTERNAL OR EXTERNAL CLOCK
CT1775 may be operated with either its internal clock or an
external clock. Internal clock operation requires that a 12 MHz
parallel-resonant
fundamental-mode
crystal,
such
as
MIL-C-3098/42 TYPE CR64/U, be connected between pin 18
(XTAL) and ground. In addition, +5 volt power must be
connected to pin 2 (OSC/CLOCK POWER), and CLOCK
OUT (pin 19) must be connected to CLOCK in (pin 24).
For external clock operation, no connection is made to pin 2
(OSC/CLOCK POWER, and the external clock is applied to
pin 24 (CLOCK IN). Pin 19 (CLOCK OUT) is not connected.
The external clock must be capable of driving a load of 20
picofarads to within 0.5 volts of the + 5 volt power supply and
to within 0.5 volts of ground. Standard TTL voltage levels will
not work properly. It must have a rise time and fall time of less
than 10 nanoseconds. For compliance with MILSTD-1553, the
external clock frequency must be 12 MHz.
8 BIT OR 16 BIT INTERFACE
The CT1775 may be configured to interface with either 8 bit or
16 bit parallel data highways. For 16 bit operation, the 16 data
lines (D 15 through DO) are used directly. LATCH DATA 1
and LATCH DATA 2 are tied together, as are DATA SELECT 1
and DATA SELECT 2. This allows data transfer in 16 bit bytes.
For 8 bit parallel data highways, the 16 data lines must be tied
together in eight pairs (1315 to D7, D8 to 130, etc.) The two
LATCH DATA and DATA SELECT are used independently.
This allows transfer in two 8 bit bytes.
ADDRESS WITH PARITY
The CT1775 provides five lines for hard-wired terminal
address. Internal pull-up resistors are provided on these lines,
so logic "1" lines may be left open-circuited. Logic "0" lines
must be grounded. The CT1775 maybe configured to check the
parity of these five address lines. This function can be selected
by using the ENA PAR CHECK line. The address parity line
(TMADDP) is hard-wired for odd address parity if the function
is sued. the ODD PARITY output flag indicates a valid check
for odd parity of the six address lines.
DUAL REDUNDANT OPERATION
The CT1775 may be used in a dual redundant configuration
with a minimum of additional circuitry. A CHAN SELECT
signal is provided which simultaneously disables the LATCH
DATA, DATA SELECT, and ENC ENABLE lines of the
CT1775. Therefore, CHAN SELECT can be used to multiplex
a single set of LATCH DATA, DATA SELECT and ENC
ENABLE control signals between two CT1775 units, which
have these signals tied together in parallel.
WRAPAROUND BUILT-IN TEST
The CT1775 may be configured to implement either on line or
off line wrap around built-in test. By enabling the receiver with
RX STROBE during a normal transmission, the encoded word
will be fed back into the decoder by the receiver. In this on line
wrap around mode of operation, the CT1775 compares each
decoded word that is fed back with the original word that was
encoded. The BIT STATUS output flag indicates when the two
words are not the same.
Care must be taken when using this on line wrap around test
technique because an outgoing status word will be interpreted
by the decoder as a new command word. Since the status word
has the correct address and the same sync as a command word,
the CT1775 will set RT ENABLE and VAL CMD WD. For on
line wrap around operation, it is therefore necessary to reset
RT ENABLE after transmission of a status word. This can be
accomplished by inverting SEND DATA and applying it to
DEC RST during status word transmission. If it is required that
the status word be fed back, RT ENABLE should be reset
immediately after it goes HIGH by applying a LOW to DEC
RST for 1 microsecond (minimum). The status word will be
available at the receive register.
The CT1775 can be placed in an off line wrap around test
mode by use of the S/T SELECT signal. In this mode, the
transceiver is disabled and the encoder output is fed directly to
the decoder input. All other functions remain the same, and the
CT1775 compares each word that is decoded with the original
word that was encoded. The BIT STATUS line also indicates
the result of this comparison for the off line wrap around test.
FAIL SAFE TIME-OUT
The CT1775 contains a timer which continuously monitors the
length of each transmitted message. This timer detects a
transmitted message which exceeds 768 microseconds and
causes the transmission to terminate. At the same time, The
FAIL-SAFE flag is set to indicate a Terminal Fail-Safe
Time-out. Further transmissions are inhibited until the
FAIL-SAFE flag is reset by MRST or a valid command word
with the correct address is received.


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