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PALCE20V8
Document #: 38-03026 Rev. **
Page 9 of 14
Functional Logic Diagram for PALCE20V8
0
1 (2)
16
20
24
28
0
12
8
4
3 (4)
22 (26)
13 (16)
20V8–9
MC7
CL1=2560
CL0=2632
4 (5)
21 (25)
MC6
CL1=2561
CL0=2633
5 (6)
20 (24)
MC5
CL1=2562
CL0=2634
6 (7)
19 (23)
MC4
CL1=2563
CL0=2635
7 (9)
18 (21)
MC3
CL1=2564
CL0=2636
8 (10)
17 (20)
MC2
CL1=2565
CL0=2637
9 (11)
16 (19)
MC1
CL1=2566
CL0=2638
10 (12)
15 (18)
MC0
CL1=2567
CL0=2639
ELECTRONIC SIGNATURE ROW
BYTE7
BYTE6 . . .
. . . BYTE1BYTE0
2568
2569 . . .
. . . 2630
2631
MSB LSB
CG0=2704
CG1=2705
23 (27)
PIN NUMBERS DIP (PLCC) PACKAGE
280
320
640
960
1280
1600
1920
2240
32
32
PTD
2 (3)
1
0
CG0
11 (13)
600
14 (17)
0
1
CG0
PIN NUMBERS DIP (PLCC)PACKAGE
920
1240
1560
1880
2200
2520