MC74HC4060A

www.onsemi.com

5

PIN DESCRIPTIONS

INPUTS

Osc In (Pin 11)

Negative−edge triggering clock input. A high−to−low

transition on this input advances the state of the counter. Osc

In may be driven by an external clock source.

Reset (Pin 12)

Active−high reset. A high level applied to this input

asynchronously resets the counter to its zero state (forcing

all Q outputs low) and disables the oscillator.

OUTPUTS

Q4—Q10, Q12−Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)

Active−high outputs. Each Qn output divides the Clock

and Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 9, 10)

Oscillator outputs. These pins are used in conjunction

with Osc In and the external components to form an

oscillator. When Osc In is being driven with an external

clock source, Osc Out 1 and Osc Out 2 must be left open

circuited. With the crystal oscillator configuration in

Figure 6, Osc Out 2 must be left open circuited.

SWITCHING WAVEFORMS

Osc In

Q

GND

90%

50%

10%

90%

50%

10%

Reset

GND

50%

Figure 1.

Figure 2.

Q

GND

50%

Osc In

50%

50%

Qn

GND

50%

Qn+1

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3.

Figure 4. Test Circuit