MC74HC4538A

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10

CIRCUIT OPERATION

Figure 11 shows the HC4538A configured in the

retriggerable mode. Briefly, the device operates as follows

(refer to Figure 10): In the quiescent state, the external

one−shot has timed out and the Q output goes low.

The following, more detailed description of the circuit

operation refers to both the logic detail (Figure 10) and the

timing diagram (Figure 11).

QUIESCENT STATE

In the quiescent state, before an input trigger appears, the

output latch is high and the reset latch is high (#1 in Figure

11). Thus the Q output (pin 6 or 10) of the monostable

multivibrator is low (#2, Figure 11).

The output of the trigger−control circuit is low (#3), and

transistors M1, M2, and M3 are turned off. The external

upper and lower reference circuit has a low output (#5).

In addition, the output of the trigger−control reset circuit

is low.

TRIGGER OPERATION

The HC4538A is triggered by either a rising−edge signal

at input A (#7) or a falling−edge signal at input B (#8), with

the unused trigger input and the Reset input held at the

voltage levels shown in the Function Table. Either trigger

signal will cause the output of the trigger−control circuit to

go high (#9).

The trigger−control circuit going high simultaneously

initiates two events. First, the output latch goes low, thus

taking the Q output of the HC4538A to a high state (#10).

Second, transistor M3 is turned on, which allows the

input of both the upper and lower reference circuit

comparator).

reference circuit (#12), the outputs of both reference circuits

will be high (#13). The trigger−control reset circuit goes high,

resetting the trigger−control circuit flip−flop to a low state

reference voltage, the lower reference circuit will go low

allowing the monostable multivibrator to be retriggered.

2

18

1

6

5

4

17

14

3

9

8

QUIESCENT

STATE

TRIGGER CYCLE

(A INPUT)

TRIGGER CYCLE

(B INPUT)

RESET

RETRIGGER

TRIGGER INPUT A

(PIN 4 OR 12)

TRIGGER INPUT B

(PIN 5 OR 11)

TRIGGER-CONTROL

CIRCUIT OUTPUT

(PIN 2 OR 14)

UPPER REFERENCE

CIRCUIT

RESET INPUT

(PIN 3 OR 13)

RESET LATCH

Q OUTPUT

(PIN 6 OR 10)

Figure 11. Timing Diagram

10

11

12

13

15

16

19

20

21

22

23

24

25

τ

13

τ

7

LOWER REFERENCE

CIRCUIT