IRU3021M

5

Rev. 1.4

07/24/01

This pin provides shutdown for all the regulators. A TTL compatible, logic level high applied

to this pin disables all the outputs and discharges the soft-start capacitor. The SD signal

turns off the synchronous MOSFET allowing body diode to conduct and discharge the

output capacitor.

This pin provides the feedback for the AGP linear regulator. The Select pin when con-

nected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for

This pin provides automatic voltage selection for the AGP switching regulator. When it is

pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V.

This pin provides the soft-start for all the regulators. An internal current source charges an

external capacitor that is connected from this pin to ground which ramps up the outputs of

the regulators, preventing the outputs from overshooting as well as limiting the input cur-

rent. The second function of the Soft-Start cap is to provide long off time (HICCUP) for the

synchronous MOSFET during current limiting.

This pin has dual function. It acts as an output of the over-voltage protection circuitry or it

can be used to program the frequency using an external resistor. When used as a fault

detector, if any of the switcher outputs exceed the OVP trip point, the Fault pin switches

to 12V and the soft-start cap is discharged. If the Fault pin is to be connected to any

external circuitry, it needs to be buffered.

This pin provides the feedback for the linear regulator that its output drive is Drive4.

This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator.

This pin is not connected internally.

This pin serves as the ground pin and must be connected directly to the ground plane.

This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.

This pin provides the feedback for the linear regulator that its output drive is Drive3.

5V supply voltage. A high frequency capacitor (0.1 to 1µF) must be placed close to this

pin and connected from this pin to the ground plane for noise free operation.

This pin provides the feedback for the synchronous switching regulator. Typically this pin

can be connected directly to the output of the switching regulator. However, a resistor

divider is recommended to be connected from this pin to Vout1 and ground to adjust the

output voltage for any drop in the output voltage that is caused by the trace resistance.

The value of the resistor connected from Vout1 to Fb1 must be less than 1000Ω.

This pin is internally connected to the under-voltage and over-voltage comparators sens-

ing the Vcore status. It must be connected directly to the Vcore supply.

This pin is connected to the Drain of the power MOSFET of the Core supply and it provides

the positive sensing for the internal current sensing circuitry. An external resistor pro-

external capacitor is placed in parallel with the programming resistor to provide high fre-

quency noise filtering.

This pin serves as the Power ground pin and must be connected directly to the ground

plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-

cally 1µF) must be connected from V12 pin to this pin for noise free operation.

Output driver for the synchronous power MOSFET for the Core supply.

This pin is connected to the source of the power MOSFET for the Core supply and it

provides the negative sensing for the internal current sensing circuitry.

Output driver for the high side power MOSFET for the Core supply.

This pin is connected to the 12V supply and serves as the power Vcc pin for the output

drivers. A high frequency capacitor (typically 1µF) must be placed close to this pin and

PGnd pin and be connected directly from this pin to the ground plane for the noise free

operation.

PIN# PIN SYMBOL

PIN DESCRIPTION

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SD

Vsen2

Select

SS

Fault / Rt

Vsen4

Drive4

NC

Gnd

Drive3

Vsen3

V5

Fb

Vsen1

OCSet

PGnd

LGate

Phase

UGate

V12