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DEVICE INFORMATION

SYSTEM CLOCK

SCKI

0.8 V

SCKI

2.0 V

T0005-07

POWER-ON RESET SEQUENCE

PCM1803

SLES125 – NOVEMBER 2004

frequency. The system clock must be supplied on SCKI (pin 15).

The PCM1803 has a system clock-detection circuit that automatically senses if the system clock is operating at

Table 1 shows the relationship of typical sampling frequency and system clock frequency, and Figure 17 shows

system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING FREQUENCY (kHz)

SYSTEM CLOCK FREQUENCY (MHz)

32

8.1920

12.2880

16.3840

24.5760

44.1

11.2896

16.9344

22.5792

33.8688

48

12.2880

18.4320

24.5760

36.8640

64

16.3840

24.5760

32.7680

49.1520

88.2

22.5792

33.8688

45.1584

–

96

24.5760

36.8640

49.1520

–

(1)

Slave mode only.

SYMBOL

PARAMETER

MIN

MAX

UNIT

System clock pulse duration, HIGH

8

ns

System clock pulse duration, LOW

8

ns

Figure 17. System Clock Timing

The PCM1803 has an internal power-on reset circuit, and initialization (reset) is performed automatically at the

reset state. Figure 18 illustrates the internal power-on reset timing and the digital output for power-on reset.

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