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AT91FR40162

2632C–ATARM–03/04

Product Overview

Power Supply

The AT91FR40162 device has two types of power supply pins:

•

VDDCORE pins that power the chip core (i.e., the AT91R40008 with its embedded

SRAM and peripherals)

•

VDDIO pins that power the AT91R40008 I/O lines and the Flash memory

An independent I/O supply allows a flexible adaptation to external component signal

levels.

Input/Output

Considerations

The AT91FR40162 I/O pads accept voltage levels up to the VDDIO power supply limit.

After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the

user with maximum flexibility. It is recommended that in any application phase, the

inputs to the microcontroller be held at valid logic levels to minimize the power

consumption.

Master Clock

The AT91FR40162 has a fully static design and works on the Master Clock (MCK), pro-

vided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is

multiplexed with a general purpose I/O line. While NRST is active, and after the reset,

the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be

programmed to use this pin as standard I/O line.

Reset

Reset restores the default states of the user interface registers (defined in the user inter-

face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch

from address zero. Except for the program counter the ARM7TDMI registers do not

have defined reset states.

NRST Pin

NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-

chronized internally to the MCK. The signal presented on MCKI must be active within

the specification for a minimum of 10 clock cycles up to the rising edge of NRST to

ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising

edge of NRST.

Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset

has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not

sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted

and the watchdog triggers the internal reset, the NRST pin has priority.

Emulation Functions

Tri-state Mode

The AT91FR40162 microcontroller provides a tri-state mode, which is used for debug

purposes. This enables the connection of an emulator probe to an application board

without having to desolder the device from the target board. In tri-state mode, all the out-

put pin drivers of the AT91R40008 microcontroller are disabled.

In tri-state mode, direct access to the Flash via external pins is provided. This enables

production Flash programming using classical Flash programmers prior to board

mounting.